NeuroSOC Development

Offer single-chip FPGA solutions, either tightly coupled with hard processing core such as ARM A7/A53 on Arria/Zynq, or full soft system based upon RISC-V RV32, RV64, and RV128 (depending upon issue-width) and incorporate with product-specific optimized neuron IP.
Emphasize mobile edge computing benefiting from unique low-power and in-situ learning capabilities.
Design and produce single-package multi-chip module with 28nm RV64, NM500, and memristor RRAM memory component.
Preliminary design for high-count aggregation on 2.5D silicon substrate.
Consider future wafer-scale possibilities for NM500 effort.
ASIC design for next generation embedded neurons, memristor, and ReRAM technologies.