Portfolio
Three broad approaches are under development. We have a business partnership to utilize proprietary digital neurons in the form of IP, which we also license for on-shore and federal purposes. Having been involved in the development process for the Berkeley RISC-V ISA, we are pairing those neurons with and open-source core to create a low-power NeuroSOC (both as a package-scale device as well as dedicated silicon), including the Linux API for access. For datacenter and HPC deployment, we are designing the second-generation NVMe acceleration hardware, targeting individual 5K neuron chips initially but expanding to wafer-scale MCMs. Several applications have been deployed on test hardware by our collaborators: industrial inspection, components of autonomous vehicle operation, and latent semantic analytics.
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V0: FPGA emulated systems
V1: Integrated package
V2: high density neurons
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Gen 1: Host-attached systems x8-x16 PCIe 
Gen 2: Rackmount 1U 1M neuron units. |